1. Field of the Invention
The present invention generally relates to an inverter circuit, and specifically to an inverter circuit capable of lowering a threshold input voltage and reducing leakage current.
2. Description of the Related Art
Recent environmental measures require energy conservation, and a technology in low-voltage operation has progressed for the purpose of achieving conservation of power in electronic circuits. In order to lower a power supply voltage of the electronic circuit, it is desirable to lower a threshold voltage of a MOS transistor used therein. However, if the threshold voltage is lowered, leakage current of the circuit increases when the MOS transistor is turned off, thereby increasing current consumption. Further, if the threshold voltage is increased, the switching rate of the MOS transistor is decreased.
In some types of signals utilized for the low-voltage operation technology, a signal level is determined based on a voltage differing from that of a typical level. In such cases, a threshold voltage is controlled based on a substrate bias effect of a MOS transistor. That is, the voltage applied to a substrate gate (or back gate) of the MOS transistor is controlled to vary between when the MOS transistor is switching and when the MOS transistor stops switching. Specifically, the threshold voltage of the MOS transistor is lowered to increase rates of switching during a switching operation, and the threshold voltage thereof is increased to reduce leakage current when the switching operation is stopped.
FIG. 6 is a diagram illustrating a circuit example of an inverter circuit according to a related art (see Japanese Laid-Open Patent Application, No. 2006-147845).
An inverter circuit 100 in FIG. 6 includes a PMOS transistor P101, an NMOS transistor N101, a resistor R101, a capacitor C101, an output node OUT and a load CL, in which the output node OUT is connected to the load CL.
In FIG. 6, when a voltage input to an input node IN is at a low level or a ground voltage Vss, the PMOS transistor P101 is turned on while the NMOS transistor N101 is turned off, thereby switching the voltage applied to the output node OUT to a high level.
In this state, since the voltages at both ends of the capacitor C101 are at the low level, electric charge is not accumulated in the capacitor C101, and a substrate gate of the NMOS transistor N101 is at the ground voltage Vss. Therefore, since the threshold voltage of the NMOS transistor N101 is high, the amount of the leakage current of the NMOS transistor N101 is small, thereby reducing current consumption of the inverter circuit 100.
When the input voltage is switched from the low level to the high level or from the ground voltage Vss to a power supply voltage Vdd, the PMOS transistor P101 is turned off while the NMOS transistor N101 is turned on, thereby switching the voltage of the output node OUT to the low level.
Since the voltage at one end of the capacitor C101 to which the input node IN is connected is switched to the high level, the capacitor C101 is charged by the application of the input voltage. Since the charged current in the capacitor C101 flows into the resistor R101, a voltage drop occurs in the resistor R101, thereby increasing the voltage at the substrate gate of the NMOS transistor N101. When the voltage of the substrate gate rises, the threshold voltage of the NMOS transistor N101 lowers due to a substrate bias effect of the NMOS transistor N101.
Thus, the NMOS transistor N101 is turned on by the application of only a small input voltage to carry out a high-rate operation.
The charging of the capacitor C101 will end when a predetermined time has elapsed since the input voltage has been switched to the high level. Since one end of the capacitor C101 in this state has a voltage the same as the input voltage at the high level, the charged current therein will not flow into the resistor R101. No voltage drop thus occurs in the resistor R101, and hence, the voltage at the substrate gate of the NMOS transistor N101 is switched to the ground voltage Vss.
When the input voltage is switched from the high level to the low level, the PMOS transistor P101 is turned on while the NMOS transistor N101 is turned off, thereby switching the voltage at the output node OUT to the high level.
Since the voltage at the one end of the capacitor C101 to which the input node IN is connected is switched to the low level, the capacitor C101 is discharged in a direction towards the input node IN. Since the current discharged from the capacitor C101 flows into the resistor R101, the voltage drop occurs in the resistor R101, thereby lowering the voltage of the substrate gate of the NMOS transistor N101 to a negative level.
When the voltage of the substrate gate lowers, the threshold voltage of the NMOS transistor N101 rises due to the substrate bias effect. However, since a time at which the voltage of the output node OUT is switched from the low level to the high level is determined based on the threshold voltage of the PMOS transistor P101, the time at which the voltage of the output node OUT is switched from the low level to the high level is almost the same as that of a typical CMOS inverter circuit.
Note that when a predetermined time has elapsed since the input voltage has been switched to the low level, discharge of the capacitor C101 will end and the voltage at the substrate gate of the NMOS transistor N101 is switched to the ground voltage Vss. Accordingly, the amount of the leakage current of the NMOS transistor N101 can be maintained almost the same as that of the typical inverter circuit.
Thus, in the inverter circuit in FIG. 6, high rates of operation can be achieved by lowering the threshold voltage of the NMOS transistor N101 when the voltage of the input node IN is switched from the low level to the high level, and an increase in the leakage current can be prevented by maintaining the voltage at the substrate gate of the NMOS transistor N101 to the ground voltage Vss when the NMOS transistor N101 is turned off.
Note that as similar to the circuit configuration in FIG. 6, there is disclosed a circuit configuration in which high rates of operation can be achieved by changing the threshold voltage of the PMOS transistor P101 when the voltage of the input node IN is switched from the high level to the low level. In addition, there is also disclosed a circuit configuration in which high rates of operation can be achieved both at voltage rise time and voltage fall time of the input node IN by changing the threshold voltage of the NMOS transistor N101 when the voltage of the input node IN is switched from the low level to the high level and changing the threshold voltage of the PMOS transistor P101 when the voltage of the input node IN is switched from the high level to the low level.
However, in the inverter circuit in FIG. 6, since the voltage of the substrate gate is suppressed via the capacitor C101 connected between the input node IN and the substrate gate, the threshold voltage can be changed only when a signal rise-up or fall exhibits a dramatic change.
Further, as shown in FIG. 6, when the inverter circuit is formed on a semiconductor chip of a silicon substrate, a parasitic diode (not shown) is formed between the substrate gate and a source of the NMOS transistor N101. An anode of the parasitic diode is located at a side of the substrate gate of the NMOS transistor N101 and a cathode thereof is located at a side of the source thereof. In the inverter circuit having the parasitic diode connected therein, when the input voltage is switched from the low level to the high level, the voltage of the substrate gate of the NMOS transistor N101 is clamped to a forward voltage of the parasitic diode. Therefore, when the input voltage exceeds the forward voltage of the parasitic diode, the input voltage charges the capacitor C101, thereby undesirably causing a large amount of current to flow into the inverter circuit to lower input impedance. In addition, since more capacitors C101 may need installing, chip areas will undesirably be increased.